What we're working on

The agent loop, and the silicon under it

Modern AI runs as a loop of many models — and today's chips waste it. Here's the loop, and the chip we're building for it.

ARCH:01 · VON NEUMANNARCH:02 · IN-MEMORYMEMORYCOMPUTEdata movement = energycompute in place — nothing moves

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The story

Two threads to bring you into our thinking

Modern AI runs as a loop of many specialist models, each taking a turn. Here's what that loop is — and why it changes what a chip should be.

01 · The basics

What is an agent loop?

Modern AI handles hard tasks by looping: instead of one model answering in a single pass, the work circles through specialist models, each doing a part before handing off. That repeating cycle is the loop.

02 · How it works

One question, a whole team of models

A task splits into steps — plan, retrieve, write, check — each handled by a different specialist model. A single session runs through four to eight of them, like a relay.

03 · What changed

AI stopped being a single model

For years an AI was one big model you prompted, and chips were built for exactly that. The field shifted to agents that route a problem through many sharper models.

04 · Where the energy goes

Moving the models burns most of the power

On today's chips a model lives in memory while the maths happens elsewhere, so every step drags its weights across the chip. Run that all session and roughly 90% of the energy goes to moving data, not thinking.

05 · The mismatch

A chip built for the wrong job

The loop punishes what a conventional chip is worst at: constantly switching models and hauling their weights back and forth. The software became a loop of many models; the silicon still assumes one.

06 · The opportunity

Build the chip around the loop

So the fix isn't a faster chip — it's a different arrangement of memory and compute, built around the loop itself. The silicon physics is how we get there.

Our research focus

The hard problems behind the chip

What it takes to make computing inside memory real — from the device physics up through the software and the silicon's ability to be trusted.

01

Multi-model silicon

Several complete models stay loaded at once, so switching is instant.

What it is

Every model stays in the room

An agent loops through four to eight specialist models a session. Phynomy keeps them all resident at once, each in its own addressable bank — instead of loading one and evicting it for the next.

How it works

Switching is an electronic select

Changing model is a bank-select signal in microseconds (indicative) — nothing to reload, because nothing was ever unloaded. The hand-off cost that dominates the loop on normal hardware becomes near-free.

What it unlocks

What an ASIC can't, a GPU overpays for

A fixed-function ASIC hosts one model; a GPU can rotate models but burns energy and latency swapping weights every step. Holding the whole team resident is the property the agent loop actually needs.

02

Analog, ADC-free computation

Keep more of the work analog, instead of paying to convert it.

What it is

The converters are the hidden cost

In-memory computing produces analog currents, which conventional designs convert to digital after every operation. Those converters can dominate the power budget — giving back much of the efficiency won inside the array.

How it works

Evaluate the surrounding math in analog

Rather than digitising after each step, Phynomy evaluates the operations that wrap the multiply — attention, softmax, GELU — in the analog domain, keeping the signal continuous instead of round-tripping through converters.

What it unlocks

The conversion overhead is designed out

Removing the per-operation conversion eliminates most of the overhead converters add in conventional in-memory designs — designed out at the architecture level rather than paid down.

03

Compilers & runtimes

A new chip is only useful if developers can reach it with the tools they have.

What it is

The software that programs the physics

A crossbar that computes with resistances and voltages isn't something to target by hand. PhynoCompile and PhynoRuntime turn a trained model into something the array can run and serve.

How it works

PhynoCompile maps, PhynoRuntime serves

PhynoCompile maps a trained model onto the array — placing weights into banks and laying out the computation. PhynoRuntime then schedules and serves them, including the microsecond switching between resident models.

What it unlocks

Speaks the API you already use

The stack sits behind an OpenAI-compatible API, so existing apps target it without a rewrite. Adopting a radically different chip becomes a change of endpoint, not a change of codebase.

04

Hardware-rooted trust

What a chip is, and what it runs, becomes verifiable in the silicon itself.

What it is

Identity baked into the silicon

Every chip carries a hardware identity rooted in a physical unclonable function — a fingerprint from tiny, unrepeatable manufacturing variations, so it can't be cloned or forged. The chip can prove which chip it is.

How it works

Post-quantum attestation of what runs

On top of that identity, post-quantum attestation lets the chip cryptographically certify what it is and what it's running, using schemes built to withstand future quantum attacks. A verifier can check the proofs remotely.

What it unlocks

Compliance becomes a property of the silicon

Where data-localisation is mandated, sovereign, verifiable inference stops being a paperwork promise and becomes provable in hardware — trust rooted in the chip, not asserted in a contract.

Where it stands

Far more thinking, for the same energy.

We haven't shipped a chip. We have a patented device, crossbar arrays measured on the bench, and independent research pointing the same way — and that's what we're building the production chip on.

~1×
a flagship GPU
~30×
Phynomy · indicative

useful work per unit of energy · indicative, from early simulation and independent research

Validated by independent labs

Independent, peer-reviewed studies validate the approach — NL-DPE reports ~28× efficiency; HaLoRA runs LLaMA-3.2 at ~3% of an A100's energy.

Patented at the core

The core dual-doped TiO₂ memristor is covered by a granted patent (Indian 431/MUM/2015), with a full SPICE model.

Made in the lab

RRAM crossbar arrays have been fabricated and measured in hardware — physical silicon, not simulation.

THE AGENT LOOP. IN SILICON.

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