The converter tax: why analog computing must stay analog

You can win the energy back inside the array and lose it again at the edge.

In-memory compute does a neural network's core operation in physics. Input voltages run across an array of resistances, currents sum down each column, and the matrix-vector multiply falls out of the circuit with almost no data movement. The output of that operation is an analog current — a continuous quantity, not a number.

Conventional designs convert it. After every operation, an analog-to-digital converter reads each column current and turns it into a digital value so the rest of the chip can use it. The maths got cheap; the reading did not. Across a large array, those converters can dominate the power budget — by some accounts the largest single block — quietly giving back much of the efficiency the array just won.

Where the energy actually goes

An ADC is not a free observer. It spends energy and area, and it scales badly: more precision costs disproportionately more power, and a high-throughput design needs many converters running constantly. So a chip can compute almost for free inside the crossbar and still post mediocre tokens per joule, because the bill moved from the multiply to the read-out. Measure only the array and the architecture looks transformative. Measure the whole datapath and the converter tax is what you see.

It gets worse in practice, because a transformer is not one matrix multiply. Between the multiplies sit attention, softmax and the GELU activation. If every one of those is computed in the digital domain, the chip converts to digital, computes, and converts back to analog for the next layer — paying the tax twice a step, over and over.

Computing in the analog domain

Phynomy's approach is to keep the signal analog for as long as it stays useful. The operations that wrap the multiply — attention, softmax, GELU — are kept in the analog domain alongside it, rather than being shipped to a digital block and back. Conversion happens only where it genuinely must, and the precision and count of those converters is treated as a first-order design problem, not an afterthought bolted to the array edge.

The aim is to design most of the conversion overhead out, so the efficiency measured at the array survives all the way to the output. That is what makes a tens-of-times gain in tokens per joule a property of the whole chip rather than of one favourable block — figures that remain indicative, drawn from early simulation and independent research. The von Neumann bottleneck and the converter tax are two ways of paying for the same thing: moving and reshaping data instead of computing. A chip built for the inference era has to refuse both.